Power Control Register
| SUSPEND | Put PHY into Suspend mode. If the PHY is enabled, this bit MUST be set before entering a low power mode (DeepSleep). Note:
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| DP_UP_EN | Enables the pull up on the DP. ‘0’ : Disable. ‘1’ : Enable. |
| DP_BIG | Select the resister value if POWER_CTL.DP_EN=‘1’. This bit is valid in GPIO. ‘0’ : The resister value is from 900 to1575Opull up on the DP. ‘1’ : The resister value is from 1425 to 3090Opull up on the DP |
| DP_DOWN_EN | Enables the ~15k pull down on the DP. |
| DM_UP_EN | Enables the pull up on the DM. The bit is valid in GPIO. The pull up resistor is disabled in not GPIO. ‘0’ : Disable. ‘1’ : Enable. |
| DM_BIG | Select the resister value if POWER_CTL.DM_EN=‘1’. This bit is valid in GPIO. ‘0’ : The resister value is from 900 to1575Opull up on the DM. ‘1’ : The resister value is from 1425 to 3090Opull up on the DM |
| DM_DOWN_EN | Enables the ~15k pull down on the DP. |
| ENABLE_DPO | Enables the single ended receiver on D+. |
| ENABLE_DMO | Enables the signle ended receiver on D-. |