Cypress Semiconductor /psoc63 /USBFS0 /USBLPM /POWER_CTL

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Interpret as POWER_CTL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SUSPEND)SUSPEND 0 (DP_UP_EN)DP_UP_EN 0 (DP_BIG)DP_BIG 0 (DP_DOWN_EN)DP_DOWN_EN 0 (DM_UP_EN)DM_UP_EN 0 (DM_BIG)DM_BIG 0 (DM_DOWN_EN)DM_DOWN_EN 0 (ENABLE_DPO)ENABLE_DPO 0 (ENABLE_DMO)ENABLE_DMO

Description

Power Control Register

Fields

SUSPEND

Put PHY into Suspend mode. If the PHY is enabled, this bit MUST be set before entering a low power mode (DeepSleep). Note:

  • This bit is invalid if the HOST bit of the Host Control 0 Register (HOST_CTL0) is ‘1’.
DP_UP_EN

Enables the pull up on the DP. ‘0’ : Disable. ‘1’ : Enable.

DP_BIG

Select the resister value if POWER_CTL.DP_EN=‘1’. This bit is valid in GPIO. ‘0’ : The resister value is from 900 to1575Opull up on the DP. ‘1’ : The resister value is from 1425 to 3090Opull up on the DP

DP_DOWN_EN

Enables the ~15k pull down on the DP.

DM_UP_EN

Enables the pull up on the DM. The bit is valid in GPIO. The pull up resistor is disabled in not GPIO. ‘0’ : Disable. ‘1’ : Enable.

DM_BIG

Select the resister value if POWER_CTL.DM_EN=‘1’. This bit is valid in GPIO. ‘0’ : The resister value is from 900 to1575Opull up on the DM. ‘1’ : The resister value is from 1425 to 3090Opull up on the DM

DM_DOWN_EN

Enables the ~15k pull down on the DP.

ENABLE_DPO

Enables the single ended receiver on D+.

ENABLE_DMO

Enables the signle ended receiver on D-.

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